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| 1. general description the lpc11d14 is a arm cortex-m0 based, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduc ed code size compared to existing 8/16-bit architectures. the lpc11d14 is a dual-chip module consisting of a lpc1114 single-chip microcontroller combined with a pcf8576d universal lcd driv er in a low-cost 100-pin package. the lcd driver provides 40 segments and supports from one to four backplanes. display overhead is minimized by an on-chip di splay ram with auto-increment addressing. the lpc11d14 operates at cpu frequencies of up to 50 mhz. the peripheral complement of the lpc11d14 includes 32 kb of flash memory, 8 kb of data memory, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 uart, up to two spi interfaces with ssp feat ures, four general purpose co unter/timers, a 10-bit adc, and up to 42 general purpose i/o pins. remark: for a functional description of the lpc1114 microcontroller see the lpc1111/12/13/14 data sheet. for a detailed description of the lcd driver see the pcf8576d data sheet. both data sheets are available on the nxp web site. 2. features and benefits ? lcd driver ? 40 segments. ? one to four backplanes. ? on-chip display ram with auto-increment addressing. ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug. ? system tick timer. ? memory: ? 32 kb on-chip flash programming memory. ? 8 kb sram. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. lpc11d14 32-bit arm cortex-m0 microcontrol ler; 32 kb fl ash and 8 kb sram; 40 segment x 4 lcd driver rev. 2 ? 23 july 2012 product data sheet
lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 2 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller ? digital peripherals: ? 42 general purpose i/o (gpio) pins with co nfigurable pull-up/pull-down resistors. in addition, a configurable open-drain mode is supported. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current output driver (20 ma) on one pin. ? high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus. ? four general purpose counter/timers with a total of four capture inputs and 13 match outputs. ? programmable windowed watchdog timer (wdt). ? analog peripherals: ? 10-bit adc with input multiplexing among 8 pins. ? serial interfaces: ? uart with fractional baud rate generation, internal fifo, and rs-485 support. ? two spi controllers with ssp features and with fifo and multi-protocol capabilities. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address reco gnition and monitor mode. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? programmable watchdog oscillator with a frequency range of 9.4 khz to 2.3 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, cpu clock, and the watchdog clock. ? power control: ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. ? power profiles residing in boot rom allowing to optimize performance and minimize power consumption for any given application through one simple function call. ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. ? power-on reset (por). ? brownout detect with four separate thre sholds for interrup t and forced reset. ? unique device serial number for identification. ? single power supply (1.8 v to 3.6 v). ? available as 100-pin lqfp100 package. lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 3 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 3. applications 4. ordering information 4.1 ordering options 5. block diagram ? industrial applications (e.g. thermostats) ? white goods ? human interface ? sensors table 1. ordering information type number package name description version LPC11D14FBD100/302 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 table 2. ordering options type number flash total sram power profiles uart rs-485 i 2 c/ fast+ spi adc channels package LPC11D14FBD100/302 32 kb 8 kb yes 1 1 2 8 lqfp100 fig 1. lpc11d14 block diagram scl, sda lcd_scl, lcd_sda v lcd lpc1114 mcu pcf8576d lcd controller pio0, pio1, pio2, pio3 s[39:0] bp[3:0] 002aag449 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 4 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller fig 2. lpc1114 block diagram sram 8 kb arm cortex-m0 test/debug interface flash 32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd lpc1114 002aag448 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wdt ioconfig ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dtr, dsr, cts, dcd, ri, rts system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap0 16-bit counter/timer 1 ct16b1_mat[1:0] ct16b1_cap0 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap0 sck0, ssel0 miso0, mosi0 sck1, ssel1 miso1, mosi1 spi1 system bus lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 5 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller fig 3. pcf8576d block diagram 40 002aag451 lcd bias generator lcd voltage selector pcf8576d backplane outputs display controller command decoder write data control display ram 40 x 4-bit output bank select and blink control display register display segment outputs data pointer and auto increment subaddress counter clock select and timing oscillator input filters blinker timebase power-on reset i 2 c-bus controller bp0 bp2 bp1 bp3 v dd(lcd) osc sync s0 to s39 lcd_sda lcd_scl clk v ss(lcd) v ss(lcd) v ss(lcd) v ss(lcd) v lcd a0 sa0 a1 a2 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 6 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning fig 4. pin configuration lqfp100 package LPC11D14FBD100/302 pio1_7 s29 pio3_3 s28 n.c. s27 pio2_6 s26 pio2_0 s25 reset/pio0_0 s24 pio0_1 s23 v ss s22 xtalin s21 xtalout s20 v dd s19 pio1_8 s18 pio0_2 s17 pio2_7 s16 pio1_9 s10 pio3_4 s9 pio2_4 s8 pio2_5 s7 pio3_5 pio2_8 pio2_1 pio0_3 pio0_4 pio0_5 s6 s15 s14 s13 s12 s11 pio0_6 s5 pio0_7 pio1_6 pio2_9 pio1_5 pio2_10 v dd s34 pio3_2 s35 pio1_11 s36 v ss s37 pio1_4 s38 swdio/pio1_3 s39 pio2_3 lcd_ sda pio3_1 lcd_ scl pio3_0 sync r/pio1_2 clk r/pio1_1 v dd(lcd) r/pio1_0 bp3 pio0_8 s0 pio2_2 s1 s33 s2 s32 s3 v ss(lcd) v lcd bp0 bp2 bp1 s31 r/pio0_11 pio2_11 pio1_10 swclk/pio0_10 pio0_9 s4 s30 002aag450 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 7 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 6.2 pin description table 3. lpc11d14 pin description table (lqfp100 package) symbol pin start logic input type reset state [1] description microcontroller pins pio0_0 to pio0_11 i/o port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 6 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital inpu t/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 7 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 13 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 17 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl 18 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 19 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 25 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 26 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 81 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 82 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 8 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller swclk/pio0_10/ sck0/ ct16b0_mat2 83 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 86 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 i/o port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ ad1/ct32b1_cap0 87 [5] yes i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 88 [5] no o i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 89 [5] no i i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 93 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 94 [5] no i/o i; pu pio1_4 ? general purpose digital inpu t/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. table 3. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 9 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller pio1_5/rts / ct32b0_cap0 99 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 100 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 1 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 12 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 20 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 84 [5] no i/o i; pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 96 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 to pio2_11 i/o port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pio2_0/dtr /ssel1 5 [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 16 [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd /miso1 80 [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 92 [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_4 22 [3] no i/o i; pu pio2_4 ? general purpose digital input/output pin. pio2_5 23 [3] no i/o i; pu pio2_5 ? general purpose digital input/output pin. pio2_6 4 [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 14 [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 15 [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_9 27 [3] no i/o i; pu pio2_9 ? general purpose digital input/output pin. table 3. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 10 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller pio2_10 28 [3] no i/o i; pu pio2_10 ? general purpose digital input/output pin. pio2_11/sck0 85 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio3_0 to pio3_5 i/o port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_6 to pio3_11 are not available. pio3_0/dtr 90 [3] no i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_1/dsr 91 [3] no i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_2/dcd 97 [3] no i/o i; pu pio3_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. pio3_3/ri 2 [3] no i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. pio3_4 21 [3] no i/o i; pu pio3_4 ? general purpose digital input/output pin. pio3_5 24 [3] no i/o i; pu pio3_5 ? general purpose digital input/output pin. v dd 11; 98 - i - 3.3 v supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 9 [6] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 10 [6] - o - output from the oscillator amplifier. v ss 8; 95 - i - ground. lcd display pins s0 46 - o v lcd [7] lcd segment output. s1 47 - o v lcd [7] lcd segment output. s2 48 - o v lcd [7] lcd segment output. s3 49 - o v lcd [7] lcd segment output. s4 50 - o v lcd [7] lcd segment output. s5 51 - o v lcd [7] lcd segment output. s6 52 - o v lcd [7] lcd segment output. s7 53 - o v lcd [7] lcd segment output. s8 54 - o v lcd [7] lcd segment output. s9 55 - o v lcd [7] lcd segment output. s10 56 - o v lcd [7] lcd segment output. s11 57 - o v lcd [7] lcd segment output. s12 58 - o v lcd [7] lcd segment output. s13 59 - o v lcd [7] lcd segment output. s14 60 - o v lcd [7] lcd segment output. s15 61 - o v lcd [7] lcd segment output. s16 62 - o v lcd [7] lcd segment output. table 3. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 11 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level (v dd = 3.3 v)); ia = inactive, no pull-up/down enabled. s17 63 - o v lcd [7] lcd segment output. s18 64 - o v lcd [7] lcd segment output. s19 65 - o v lcd [7] lcd segment output. s20 66 - o v lcd [7] lcd segment output. s21 67 - o v lcd [7] lcd segment output. s22 68 - o v lcd [7] lcd segment output. s23 69 - o v lcd [7] lcd segment output. s24 70 - o v lcd [7] lcd segment output. s25 71 - o v lcd [7] lcd segment output. s26 72 - o v lcd [7] lcd segment output. s27 73 - o v lcd [7] lcd segment output. s28 74 - o v lcd [7] lcd segment output. s29 75 - o v lcd [7] lcd segment output. s30 76 - o v lcd [7] lcd segment output. s31 77 - o v lcd [7] lcd segment output. s32 78 - o v lcd [7] lcd segment output. s33 79 - o v lcd [7] lcd segment output. s34 29 - o v lcd [7] lcd segment output. s35 30 - o v lcd [7] lcd segment output. s36 31 - o v lcd [7] lcd segment output. s37 32 - o v lcd [7] lcd segment output. s38 33 - o v lcd [7] lcd segment output. s39 34 - o v lcd [7] lcd segment output. bp0 42 - o v lcd [7] lcd backplane output. bp1 44 - o v lcd [7] lcd backplane output. bp2 43 - o v lcd [7] lcd backplane output. bp3 45 - o v lcd [7] lcd backplane output. lcd_sda 35 - i/o [7] i 2 c-bus serial data input/output. lcd_scl 36 - i/o [7] i 2 c-bus serial clock input. sync 37 - i/o [7] cascade synchronization input/output. clk 38 - i/o [7] external clock input/output. v dd(lcd) 39 - - - 1.8 v to 5.5 v power supply: power supply voltage for the pcf8576d. v ss(lcd) 40 - - - lcd ground. the pcf8576 input signals a0, a1, a2, sa0, and osc are internally hard-wired to v ss(lcd) . v lcd 41 - - - lcd power supply; lcd voltage. n.c. 3 - - - not connected. table 3. lpc11d14 pin description table (lqfp100 package) ?continued symbol pin start logic input type reset state [1] description lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 12 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller [2] reset functionality is not available in deep power-down mode. us e the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of t he pad is disabled and the pin is not 5 v tolerant. [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. [7] see section 7.2.3 . lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 13 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 lpc1114 microcontroller see ref. 1 for a detailed functional description of the lpc1114 microcontroller. 7.2 lcd driver see ref. 2 for a detailed functional description of the pcf8576d lcd driver. 7.2.1 general description the pcf8576d is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it gene rates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 40 segments. it can be easily cascaded for larger lcd applications. the pcf8576d communicates via the two-line bidirectional i 2 c-bus. communication overheads are mi nimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). please refer to pcf8576d data sheet for electrical data. 7.2.2 functional description the pcf8576d is a versatile peripheral device interfacing the lpc1114 microcontroller with a wide variety of lcds. it can directly dr ive any static or multiplexed lcd containing up to four backplanes and up to 40 segments. the possible display configurations of the pcf8576d depend on the number of active backplane outputs required. a selection of display configurations is shown in table 4 . the integration of the lpc1114 microcontr oller with the pcf8576d is shown in figure 1 . 7.2.3 reset state of the lcd controller and pins after power-on, the lcd controller resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd . ? the selected drive mode is 1:4 multiplex with 1/3 bias. ? blinking is switched off. ? input and output bank selectors are reset. ? the i 2 c-bus interface is initialized. ? the data pointer and the subaddress counter are cleared (set to logic 0). ? the display is disabled. table 4. selection of display configurations number of digits/characters backplanes segments 7-segment 14-segment dot matrix/elements 4 160 20 10 160 (4 ? 40) 3 120 15 7 120 (3 ? 40) 2 80 10 5 64 (2 ? 40) 14 0524 0 ( 1 ? 40) lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 14 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2.4 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss(lcd) . the middle resistor can be bypassed to provide a 1/2 bias voltage level for the 1:2 mult iplex configuration. the lcd voltage can be temperature compensated externally using the supply to pin v lcd . 7.2.5 oscillator 7.2.5.1 internal clock the internal logic of the pcf8576d and the lc d drive signals are timed by the internal oscillator. the internal oscilla tor is always enabled. the out put from pin clk can be used as the clock signal for several pcf8576ds in the system that are connected in cascade. 7.2.6 timing the pcf8576d timing controls the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pcf8576d in the system is maintained by the synchron ization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency (f fr ) is a fixed division of the clock frequency (f clk ) from either the internal or an external clock: f fr = f clk /24. 7.2.7 display register a display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationshi p between the data in the display latch, the lcd segment outputs, and each column of the display ram. 7.2.8 segment outputs the lcd drive section includes 40 segment outpu ts s0 to s39 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backp lane signals and with data residing in the display latch. when less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.2.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1:2 multiplex drive mode, bp0 and bp2, bp1 and bp3 all carry the same signals and may also be paired to in crease the drive capabilities. lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 15 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller in the static drive mode the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.2.10 display ram the display ram is a static 40 ? 4-bit ram which stores lcd data. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. for details, see ref. 2 . lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 16 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) 1.8 3.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] ? 0.5 +5.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c - 100 ma t stg storage temperature non-operating [3] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [4] ? 6500 +6500 v lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 17 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 9. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.8 3.3 3.6 v power consumption in low-current mode [10] i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -2-m a system clock = 50 mhz v dd = 3.3 v [2] [3] [5] [6] [7] -7-m a sleep mode; system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] -1-m a deep-sleep mode; v dd = 3.3 v [2] [3] [8] -2- ? a deep power-down mode; v dd = 3.3 v [2] [9] -2 2 0-n a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 10 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled - 0.5 10 na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled - 0.5 10 na v i input voltage pin configured to provide a digital function [11] [12] [13] 0- 5 . 0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.5 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4--v 1.8 v ? v dd < 2.5 v; i oh = ? 3 ma v dd ? 0.4--v v ol low-level output voltage 2.5 v ? v dd ? 3.6 v; i ol =4 ma --0 . 4v 1.8 v ? v dd < 2.5 v; i ol =3 ma --0.4v lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 18 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller i oh high-level output current v oh =v dd ? 0.4 v; 2.5 v ? v dd ? 3.6 v ? 4--m a 1.8 v ? v dd < 2.5 v ? 3--ma i ol low-level output current v ol =0.4v 2.5 v ? v dd ? 3.6 v 4--m a 1.8 v ? v dd < 2 . 5 v 3--m a i ohs high-level short-circuit output current v oh =0v [14] --? 45 ma i ols low-level short-circuit output current v ol =v dd [14] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 21 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 5. adc characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb = lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 22 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 9.1 bod static characteristics [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc111x user manual . 9.2 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc111x user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. table 8. bod static characteristics [1] t amb =25 ?c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.65 - v de-assertion - 1.80 - v interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 23 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resistors di sabled; bod disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 6. active mode: typical supply current i dd versus supply voltage v dd for different system clock frequencies conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register (sysah bclkctrl = 0x1f); a ll peripheral clocks disabled; internal pull-up resistors di sabled; bod disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 7. active mode: typical supply current i dd versus temperature for different system clock frequencies v dd (v) 1.8 3.6 3.0 2.4 002aaf980 4 6 2 8 10 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aaf981 temperature ( c) ?40 85 35 10 60 ?15 2 8 6 4 10 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 24 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 8. sleep mode: typical supply current i dd versus temperature for different system clock frequencies temperature ( c) ?40 85 35 10 60 ?15 002aaf982 2 4 6 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 25 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 9. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd fig 10. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd 002aaf977 temperature ( c) ?40 85 35 10 60 ?15 2.5 4.5 3.5 5.5 i dd (a) 1.5 v dd = 3.3 v, 3.6 v 1.8 v 002aaf978 0.2 0.6 0.4 0.8 i dd (a) 0 temperature ( c) ?40 85 35 10 60 ?15 v dd = 3.6 v 3.3 v 1.8 v lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 26 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 9.3 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. table 9. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.27 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.22 - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.004 - - system oscillator running; pll off; independent of main clock frequency. bod 0.051 - - independent of main clock frequency. main pll - 0.21 - adc - 0.08 0.29 clkout - 0.12 0.47 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.02 0.06 ct16b1 - 0.02 0.06 ct32b0 - 0.02 0.07 ct32b1 - 0.02 0.06 gpio - 0.23 0.88 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. ioconfig - 0.03 0.10 i2c - 0.04 0.13 rom - 0.04 0.15 spi0 - 0.12 0.45 spi1 - 0.12 0.45 uart - 0.22 0.82 wdt - 0.02 0.06 main clock selected as clock source for the wdt. lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 27 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 9.4 electrical pi n characteristics conditions: v dd = 3.3 v; on pin pio0_7. fig 11. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 12. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 28 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 13. typical low-l evel output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins. fig 14. typical high-level output voltage v oh versus high-level output source current i oh v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 29 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 15. typical pull-up current i pu versus input voltage v i conditions: v dd = 3.3 v; standard port pins. fig 16. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 30 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 power-up ramp conditions [1] see figure 17 . [2] the wait time specifies the time the power supply must be at levels below 400 mv before ramping up. 10.2 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. table 10. power-up characteristics t amb = ? 40 ? c to +85 ?c. symbol parameter conditions min typ max unit t r rise time at t = t 1 : 0 < v i ?? 400 mv [1] 0- 500 ms t wait wait time [1] [2] 12 - - ? s v i input voltage at t = t 1 on pin v dd 0 - 400 mv condition: 0 < v i ?? 400 mv at start of power-up (t = t 1 ) fig 17. power-up ramp v dd 0 400 mv t r t wait t = t 1 002aag001 table 11. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 31 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 10.3 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 12. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ?c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 18. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 32 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 10.4 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc111x user manual . table 13. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 19. internal rc oscillator frequency versus temperature table 14. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 33 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 10.5 i/o pins [1] applies to standard port pins and reset pin. 10.6 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. table 15. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 16. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ?c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 34 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. 10.7 spi interfaces fig 20. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 17. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns t ds data set-up time in spi mode 2.4 v ? v dd ? 3.6 v [2] 15 - - ns 2.0 v ? v dd < 2.4 v [2] 20 ns 1.8 v ? v dd < 2.0 v [2] 24 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 35 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to +85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd = 3.3 v. spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns table 17. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 21. spi master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 36 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 22. spi slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 37 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 11. application information 11.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 7 : ? the adc input trace must be short and as close as possible to the lpc11d14 chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 11.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv (rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 23 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 24 and in ta b l e 1 8 and ta b l e 1 9 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 24 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 1 8 ). fig 23. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 38 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 11.3 xtal printed circuit bo ard (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in fig 24. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 18. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 19. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 39 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 11.4 standard i/o pad configuration figure 25 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 25. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aah159 pin configured as digital output driver pin configured as digital input pin configured as analog input lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 40 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 11.5 reset pad configuration 11.6 electromagnetic co mpatibility (emc) radiated emission measurements according to the iec 61967-2 standard using the tem-cell method are shown for the lpc1114fbd48/302 in ta b l e 2 0 . [1] iec levels refer to appendix d in the iec 61967-2 specification. fig 26. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin table 20. electromagnetic compatibility (e mc) for part lpc1114fbd48/302 (tem-cell method) v dd = 3.3 v; t amb = 25 ? c. parameter frequency band system clock = unit 12 mhz 24 mhz 48 mhz input clock: irc (12 mhz) maximum peak level 150 khz - 30 mhz ? 7 ? 5 ? 7db ? v 30 mhz - 150 mhz ? 21 1 0d b ? v 150 mhz - 1 ghz 4 8 16 db ? v iec level [1] -onm- input clock: crystal oscillator (12 mhz) maximum peak level 150 khz - 30 mhz ? 7 ? 7 ? 7db ? v 30 mhz - 150 mhz ? 218db ? v 150 mhz - 1 ghz 4 7 14 db ? v iec level [1] -onm- lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 41 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 12. package outline fig 27. package outline (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1)(1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 42 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 13. soldering fig 28. reflow soldering of the lqfp100 package sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550 lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 43 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 14. abbreviations 15. references [1] lpc1111/12/13/14 data sheet [2] pcf8576d data sheet table 21. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection gpio general purpose input/output pll phase-locked loop rc resistor-capacitor spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tem transverse electromagnetic uart universal asynchronous receiver/transmitter lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 44 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 16. revision history table 22. revision history document id release date data sheet status change notice supersedes lpc11d14 v.2 20120723 product data sheet - lpc11d14 v.1 modifications: ? figure 3 updated. ? internal oscillator description updated ( section 7.2.5 ). ? description of the v ss(lcd) pin updated in table 3 . ? data sheet status changed to product data sheet. ? remove table note ?the peak current is limited to 25 times the corresponding maximum current? in ta b l e 5 . ? for parameters i ol , v ol , i oh , v oh , changed conditions to 1.8 v ? v dd < 2.5 v and 2.5 v ? v dd ? 3.6 v in ta b l e 6 . ? figure 25 updated for parts with configurable open-drain mode. ? wdosc frequency range corrected. lpc11d14 v.1 20110928 preliminary data sheet - - lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 45 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. lpc11d14 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 23 july 2012 46 of 47 nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors lpc11d14 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 23 july 2012 document identifier: lpc11d14 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 13 7.1 lpc1114 microcontroller. . . . . . . . . . . . . . . . . 13 7.2 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.1 general description . . . . . . . . . . . . . . . . . . . . 13 7.2.2 functional description. . . . . . . . . . . . . . . . . . . 13 7.2.3 reset state of the lcd controller and pins . . . 13 7.2.4 lcd bias generator . . . . . . . . . . . . . . . . . . . . 14 7.2.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.2.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.2.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 9 static characteristics. . . . . . . . . . . . . . . . . . . . 17 9.1 bod static characteristics. . . . . . . . . . . . . . . . 22 9.2 power consumption . . . . . . . . . . . . . . . . . . . . 22 9.3 peripheral power consumptio n . . . . . . . . . . . . 26 9.4 electrical pin characteristics . . . . . . . . . . . . . . 27 10 dynamic characteristics . . . . . . . . . . . . . . . . . 30 10.1 power-up ramp conditions . . . . . . . . . . . . . . . 30 10.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.4 internal oscillators. . . . . . . . . . . . . . . . . . . . . . 32 10.5 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.6 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.7 spi interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 application information. . . . . . . . . . . . . . . . . . 37 11.1 adc usage notes . . . . . . . . . . . . . . . . . . . . . . 37 11.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.3 xtal printed circu it board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.4 standard i/o pad configuration . . . . . . . . . . . . 39 11.5 reset pad configuration . . . . . . . . . . . . . . . . . 40 11.6 electromagnetic compatibility (emc) . . . . . . . 40 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 41 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 43 15 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 44 17 legal information . . . . . . . . . . . . . . . . . . . . . . 45 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 45 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46 18 contact information . . . . . . . . . . . . . . . . . . . . 46 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 |
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